In a static random access memory (SRAM) cell, one-bit is formed by a flip-flop structure. Therefore, the inverter output portion of one transistor is put in contact with the gate of the other transistor. The inverter output portion of the other transistor is put in contact with the gate of the first-mentioned transistor. This is particularly called "coupling".
In manufacturing an LSI, the output portion of the inverter corresponds to the drain portion (N.sup.+ diffusion region) of a driver transistor (hereinafter, referred to as "pull-down transistor"). Therefore, the N.sup.+ diffusion region must be brought into contact with the gate, to effect coupling.
The direct contact is made as shown in FIG. 18. A polysilicon layer P1 for forming a gate G1 of a transistor Q1 extends to the proximity of a drain D2 of a transistor Q2 and comes into contact with the drain D2, and a polysilicon layer P2 of the transistor Q2 extends, in a similar fashion, to the proximity of a drain D1 of the transistor Q1. As a result, a source S serving as a ground electrode is surrounded by polysilicon layers. Therefore, another layer must be provided for the formation of the ground wiring L. That is, an additional polysilicon layer or an extra silicide layer (TiSi.sub.2, WSi) is further required.
For making the coupling, the following conventional methods are known: (1) coupling is made by a second polysilicon layer and not by a first polysilicon layer forming the gate, and (2) coupling is made by a direct contact of the gate polysilicon of one transistor and the N+ diffusion region of the other transistor.
In the method (1), after completion of a source/drain formation step by means of a CMOS process, an insulating film is removed from the gate polysilicon of one transistor and from the N.sup.+ diffusion region of the other transistor, and then, a Ti silicide layer is formed thereon. Subsequently, a second polysilicon layer is formed on the resultant structure. By way of the second polysilicon layer thus formed, the gate polysilicon of one transistor is coupled with the N.sup.+ diffusion region of the other transistor.
However, this method has a drawback. Since three masks are required, the manufacturing process becomes complicated. Furthermore, to form contact on the gate polysilicon, the gate polysilicon must be overlapped with a contact pattern, increasing a cell size. To prevent the enlargement of the cell-size, a technique such as self-align contact is required. If so, the manufacturing steps will further increase, complicating the manufacturing process. Furthermore, this method requires to form two types of contacts. Therefore, the process corresponding to each of ohmic contacts must be controlled.
In the method (2), after the gate oxide film is removed from the contact formation portion of a substrate, a gate polysilicon layer is formed. Subsequently, phosphorus glass is deposited on the gate polysilicon layer and heat treatment is applied to the resultant structure. As a result, phosphorus is diffused not only into the polysilicon layer but also into the contact formation region of the substrate. In this manner, the direct contact of gate polysilicon with the N.sup.+ diffusion region can be attained.
However, this method has a drawback. Since phosphorus is doped by means of heat diffusion, the phosphorus-diffusion region becomes as large as 0.5 to 1.2 .mu.m. Hence the device thus obtained cannot be used as a submicron device.